Alan Hastings， 美国TI（德州仪器）教授级工程师，具有渊博的集成电路版图设计知识和丰富的实践经验。Alan Hastings， 美国TI（德州仪器）教授级工程师，具有渊博的集成电路版图设计知识和丰富的实践经验。
Alan Hastings， 美国TI（德州仪器）教授级工程师，具有渊博的集成电路版图设计知识和丰富的实践经验。
目錄：
Contents
目 录
Chapter 1 Device Physics 器件物理 1
1.1 Semiconductors 半导体 1
1.1.1 Generation and Recombination 产生与复合 4
1.1.2 Extrinsic Semiconductors 非本征（杂质）半导体 6
1.1.3 Diffusion and Drift 扩散和漂移 9
1.2 PN Junctions PN结 11
1.2.1 Depletion Regions 耗尽区 11
1.2.2 PN Diodes PN结二极管 13
1.2.3 Schottky Diodes 肖特基二极管 16
1.2.4 Zener Diodes 齐纳二极管 18
1.2.5 Ohmic Contacts 欧姆接触 19
1.3 Bipolar Junction Transistors 双极型晶体管 21
1.3.1 Beta 值 23
1.3.2 I-V Characteristics I-V特性 24
1.4 MOS Transistors MOS晶体管 25
1.4.1 Threshold Voltage 阈值电压 27
1.4.2 I-V Characteristics I-V特性 29
1.5 JFET Transistors JFET晶体管 32
1.6 Summary 小结 34
1.7 Exercises 习题 35
Chapter 2 Semiconductor Fabrication 半导体制造 37
2.1 Silicon Manufacture 硅制造 37
2.1.1 Crystal Growth 晶体生长 38
2.1.2 Wafer Manufacturing 晶圆制造 39
2.1.3 The Crystal Structure of Silicon 硅的晶体结构 39
2.2 Photolithography 光刻技术 41
2.2.1 Photoresists 光刻胶 41
2.2.2 Photomasks and Reticles 光掩模和掩模版 42
2.2.3 Patterning 光刻 43
2.3 Oxide Growth and Removal 氧化物生长和去除 43
2.3.1 Oxide Growth and Deposition 氧化物生长和淀积 44
2.3.2 Oxide Removal 氧化物去除 45
2.3.3 Other Effects of Oxide Growth and Removal 氧化物生长和去除的其他效应 47
2.3.4 Local Oxidation of Silicon LOCOS 硅的局部氧化 49
2.4 Diffusion and Ion Implantation 扩散和离子注入 50
2.4.1 Diffusion 扩散 51
2.4.2 Other Effects of Diffusion 扩散的其他效应53
2.4.3 Ion Implantation 离子注入 55
2.5 Silicon Deposition and Etching 硅淀积和刻蚀 57
2.5.1 Epitaxy 外延 57
2.5.2 Polysilicon Deposition 多晶硅淀积 59
2.5.3 Dielectric Isolation 介质隔离 60
2.6 Metallization 金属化 62
2.6.1 Deposition and Removal of Aluminum 铝淀积及去除 63
2.6.2 Refractory Barrier Metal 难熔阻挡金属 65
2.6.3 Silicidation 硅化 67
2.6.4 Interlevel Oxide, Interlevel Nitride, and Protective Overcoat
4.3.4 Negative Bias Temperature Instability 负偏置温度不稳定性 154
4.3.5 Parasitic Channels and Charge Spreading 寄生沟道和电荷分散 156
4.4 Parasitics 寄生效应 164
4.4.1 Substrate Debiasing 衬底去偏置
內容試閱：
Preface to the Second Edition
I originally wrote The Art of Analog Layout as a companion volume to a series of lectures. Many people encouraged me to publish it. At first I was reluctant to do so, for I thought that it would find a rather limited audience. Publication has proven my concerns quite unfounded. To my astonishment, The Art of Analog Layout has even been translated into Chinese!
The passage of several years has alerted me to the limitations of the first edition and prompted an extensive revision. Every chapter has been examined and corrected. Many new passages have been added, along with some 50 new illustrations to accompany them. New topics introduced in the second edition include the following：
●Advanced metallization systems
●Dielectric isolation
●Failure mechanisms of MOS transistors
●Integrated inductors
●MOS safe operating area
●Nonvolatile memory
In preparing this edition, I have drawn extensively upon the experience and wisdom of my colleagues at Texas Instruments. I have also made constant reference to the resources available upon the IEEE Xplore website, most particularly those contained in the IEEE Journal of Electron Devices. I thank all the many people who have contributed to my own understanding or who have corrected my many mistakes. A work of this length and magnitude will never prove perfect, but the second edition greatly improves upon the first.
Alan Hastings
译文
The Art of Analog Layout一书的初稿是用于一系列讲座的。很多人鼓励我将其出版。刚开始我有点犹豫，因为我认为读者非常有限。出版之后证明了我的担心是多余的。令我惊讶的是，这本书居然被翻译成了中文！
过去的几年时间提醒我第一版存在的局限性，并且促成了这次全面的修订。本书的每一章都经过了检查和校正，并且还加入了很多新内容和约50个新的图例。第二版的新内容包括：
●先进金属化系统
●介质隔离
●MOS晶体管的失效机制
●集成电感
●MOS安全工作区
●非易失性存储器
在准备本书第二版期间，我从德州仪器公司的同事那里汲取了大量的经验和智慧。同时我还经常参考IEEE Xplore网站的可用资源，尤其是IEEE Journal of Electron Devices上的文献。我要向所有帮助我加深理解或帮助我纠正错误的人们表示感谢。如此长时间、大强度的工作虽然无法使每件事都做到完美，但是第二版确实比第一版有了很大的进步。
Preface to the First Edition
An integrated circuit reveals its true appearance only under high magnification. The intricate tangle of microscopic wires covering its surface and the equally intricate patterns of doped silicon beneath it, all follow a set of blueprints called a layout. The process of constructing layouts for analog and mixed-signal integrated circuits has stubbornly defied all attempts at automation. The shape and placement of every polygon requires a thorough understanding of the principles of device physics, semiconductor fabrication, and circuit theory. Despite 30 years of research, much remains uncertain. What information there is lies buried in obscure journal articles and unpublished manuscripts. This textbook assembles that information between a single set of covers. While primarily intended for use by practicing layout designers, it should also prove valuable to circuit designers who desire a better understanding of the relationship between circuits and lavouts.
The text has been written for a broad audience, some of whom have had only limited exposure to higher mathematics and solid-state physics. The amount of mathematics has been kept to an absolute minimum, and care has been taken to identify all variables and to use the most accessible units. The reader need only have a familiarity with basic algebra and elementary electronics. Many of the exercises assume that the reader also has access to layout editing software; but those who lack such resources can complete many of the exercises with pencil and paper.
The text consists of 14 chapters and five appendices. The first two chapters provide an overview of device physics and semiconductor processing. These chapters avoid mathematical derivations and instead emphasize simple verbal explanations and visual models. The third chapter presents three archetypal processes： standard bipolar, silicon-gate CMOS, and analog BiCMOS. The presentation focuses upon development of cross sections and the correlation of these cross sections to conventional layout views of sample devices. The fourth chapter covers common failure mechanisms and emphasizes the role of layout in determining reliability. Chapters 5 and 6 cover the layout of resistors and capacitors.
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